QDI Implementations of Boolean Graphs

Implementing combinational logic efficiently in QDI designs is hard, due to the need to acknowledge every transition, and naive approaches are often used. The paper demonstrates the problem of using Delay-Insensitive Minterm Synthesis on anything but the smallest designs.These problems can be overcome by employing techniques from MultiLevel Logic synthesis. An initial method using Roth-Karp decomposition is described. 1. Delay-Insensitive Circuits Delay-insensitive circuits make no assumptions about the delays within either the circuit or its environment, except that they are finite and positive. As such they are more robust than other circuit styles whose operation is based on (and optimised for) worst case constraints. Apart from this increased operating ability, delay insensitivity has many other advantages: • DI circuits need no timing validation once they are designed. Circuit styles such as single-rail can only be validated by comprehensive simulation. • DI circuits can be scaled to any process easily and are not constrained by layout timing issues. These factors make delay insensitivity particularly desirable in a synthesis environment as it allows designers to produce designs that need little post-layout verification, can be ported between technologies with ease and surrendered to automatic place and route software without any danger of it breaking delay assumptions. However, eliminating the assumptions made in a design also has its costs. Delay-insensitive circuits: • generally face extra overheads in area due to the need to disseminate timing information throughout the circuit. • usually have higher power consumption due to the need to transmit data validity explicitly • may suffer a speed penalty due to the extra logic and switching involved in their operation. In order for a circuit to be DI certain conditions must be upheld [4]: • Stability Once the conditions that allow a gate to transition (guards) are met, they cannot be falsified before the gate has transitioned • Non-Interference The two guards of any gate must be mutually-exclusive. In order to uphold these conditions Martin defined two properties all DI circuits must adhere to: • Acknowledgement Theorem Each non-final transition in a circuit must be acknowledged by a subsequent transition. • Unique Successor Set Theorem The set of nodes that transition as a result of a transition on a node, x, must be unique and the same for both up-going and down-going transitions on that node. In practice these properties are so restrictive that no practical DI circuits can be built. So Martin suggested the weakest compromise to delay-insensitivity, the isochronic fork. An isochronic fork is a fork where only one transition need be explicitly acknowledged, with the assumption that if a transition is seen on one end of the fork, it will also have appeared on the other end. Circuits implementing isochronic forks are called Quasi-Delay-Insensitive (QDI) circuits. Research [11] suggests that isochronic fork assumptions need careful verification and can be violated by mismatched threshold voltages or gate capacitances on the receiving gates. Isochronic forks can be extended through gates, resulting in QnDI circuits, where n is the number of gates through which an unacknowledged signal travels. QnDI circuits often employ asymmetric forks, where a path a deemed to be slower as it travels through less gates. Again [11] showed that these assumptions need careful verification as their operation is not always predictable. Theseus Logic Inc. [3] extended the notion of isochronic forks and extended isochronic forks, and traded the unacknowledged path against the cycle time of the circuit. These assumptions are known as Orphans. Data in QDI systems is encoded in a delay-insensitive, or unordered, code[12]. This encodes validity directly into the data, eliminating the assumptions necessary in transmitting a valid signal separately. There are many DI codes, the simplest are the one-hot codes, where a single transition on a wire represents the arrival of valid data, with a set of n wires representing n values.The efficiency of such a code can be increased by concatenating many such codes together into a larger code called a 1-of-n. This idea can be generalised to an m-of-n code where transitions upon m wires from a set of n represents the arrival of valid data. Often the Rate (number of data symbols per wire) of a datapath can be increased by employing m-of-n codes (m>1), but the logic is generally more complicated due to the encoding complexity. 2. Combinational Logic in QDI Systems Implementing QDI logic is generally more complicated than in other design styles as traditional optimisation techniques cannot, in general, be used, as these techniques make use of don’t care values to try and reduce the size of implementations. In a QDI circuit, if a transition has no part to play in the output of a function, it becomes unacknowledged and therefore introduces extra assumptions into the circuit. 2.1. Delay-Insensitive Minterm Synthesis A very simple method for performing logic in QDI circuits is called Delay-Insensitive Minterm Synthesis (DIMS)[10]. Here the function is implemented by a simple S-O-P of all the valid products. It should be noted that in Return-To-Zero DI systems, the spacer (zero) value of a wire represents an absence of data on that wire, so all products are generated with only the active literals in that value, and there are no inverters. To correctly acknowledge the return-to-zero phase of the circuit, each product is instantiated with a c-element. Because each product is unique only one c-element will be activated in any cycle and will be properly acknowledged by the or-gate network. The circuit is QDI, the only assumption being the fan-out of the inputs to multiple gates. This method, because of its simplicity, is very easy to use for the synthesis of general function and has become popular[]. It’s main drawback is its size, which increases exponentially with function size. However, the DIMS technique can become invalid for QDI networks employing complex codes or a number of input code groups. In a DIMS function each product is unique as it is implemented by a single gate element. However, for anything but the simplest functions, fan-in restrictions mean the products have to be decomposed over several gates (fig1). When the products are decomposed, the products cease to be unique as the partial products may be shared amongst several products as in fig 1. This means when an input set is applied to the circuit several intermediate gates will be activated, but only one product will actually fire, leaving several unacknowledged transitions on the gates of the unactivated products, resulting in QnDI circuits. Clearly this problem increases with the use of m-of-n codes and increased inputs, causing further decompositions, and possibly shared trees of c-elements. This results in dangerous Orphan assumptions, particularly in synthesis systems where the amount of sharing is not known, and may go unchecked. The problem can be solved by sharing common partial products between all the products. This problem is similar to extracting common divisors in multi-level logic synthesis, with the extra constraint that all common products must be shared. A simple example of how traditional synthesis techniques may be used to implement QDI circuits is given below. 3. Functional Decomposition Functional decomposition was first suggested by R.L. Ashenhurst in the 1950’s [1], and can be thought of as transforming a function, f(X), to the form (fig) where X is as set of variables {X1,X2,...,Xn} and Y and Z are subsets of X. Y is known as the bound set of X and Z the free set. The function g is known as the image. The idea behind the decomposition is to calculate a set of compatible classes from the input vectors of Y, which are encoded in the outputs of the function α. Ashenhurst describes a simple, disjoint decomposition where Y and Z are disjoint and the α function only yields a single binary value. Ashenhurst’s method involved generating a partition matrix, which contains an entry for all possible values of the Y and Z sets. The matrix is reduced to remove all duplicate rows and columns. Ashenhurst stated that for a simple decomposition to exist a partition matrix must have a most two distinct columns. The notion of decomposition was extended by J. P. Roth & Figure 1: Decomposed DIMS Dual-Rail Full Adder Figure 2: General Function Decomposition C C